SH7144_08 Datasheet, PDF (164/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

8. Data Transfer Controller (DTC)
8.2.8 DTC Control/Status Register (DTCSR)
DTCSR is a 16-bit readable/writable register that is used to disable/enable DTC activation by
software and to set the DTC vector addresses for software activation. It also indicates the DTC
transfer status.
Bit Bit Name
15 to —
11
10 NMIF
Initial Value
All 0
0
R/W Description
R
Reserved
These bits have no effect on DTC operation. The
write value should always be 0.
R/(W)*¹ NMI Flag Bit
This bit indicates that an NMI interrupt has occurred.
0: No NMI interrupts
[Clearing condition]
• Write 0 after reading the NMIF bit
9
AE
0
1: NMI interrupt has been generated
When the NMIF bit is set, DTC transfers are not
allowed even if the DTER bit is set to 1. If, however,
a transfer has already started with the NMIM bit of
the DTMR set to 1, execution will continue until that
transfer ends.
R/(W)*¹ Address Error Flag
This bit indicates that an address error by the DTC
has occurred.
0: No address error by the DTC
[Clearing condition]
• Write 0 after reading the AE bit
8
SWDTE 0
R/W*²
1: An address error by the DTC occurred
When the AE bit is set, DTC transfers are not
allowed even if the DTER bit is set to 1.
DTC Software Activation Enable
Setting this bit to 1 activates DTC.
0: DTC activation by software disabled
1: DTC activation by software enabled
Rev.4.00 Mar. 27, 2008 Page 120 of 882
REJ09B0108-0400