SH7144_08 Datasheet, PDF (541/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
Start
Initial setting
Read the BBSY flag in ICCR
No
BBSY = 0?
Yes
Set MST = 1
and TRS = 1 (ICCR)
Write BBSY= 1
and SCP = 0 (ICCR)
Read the IRIC flag in ICCR
No
IRIC = 1?
Yes
Write transmit data to ICDR
Clear the IRIC flag in ICCR
Read the IRIC flag in ICCR
No
IRIC = 1?
Yes
Read the ACKB bit in ICSR
ACKB = 0?
No
Yes
Transmit mode? ^No
Yes
Write data for transmission to ICDR
Clear the IRIC flag in ICCR
Read the IRIC flag in ICCR
No
IRIC = 1?
Yes
Read the ACKB bit in ICSR
No
Transmission
completed?
(ACKB = 1?)
Yes
Clear the IRIC flag in ICCR
Write 0 to the ACKE bit
in ICCR
Write BBSY = 0
and SCP = 0 (ICCR)
End
[1] Initial setting
[2] Determine the states of the SCL and SDA lines.
[3] Set master transmit mode
[4] Start condition issuance
[5] Wait for the start condition generation
[6] Set transmit data for the first byte (slave address + R/ W)
(After writing to ICDR, clear IRIC sequentially)
[7] Wait for 1 byte to be transmitted.
[8] Determine the acknowledge bit transferred from the
specified slave device.
Master receive mode
[9] Set transmit data for the second and subsequent bytes.
(After writing to ICDR, clear IRIC sequentially)
[10] Wait for 1 byte to be transmitted.
[11] Determine the end of transfer
[12] Stop condition issua
Figure 14.7 Example: Flowchart of Operations in the Master Transmit Mode
Rev.4.00 Mar. 27, 2008 Page 497 of 882
REJ09B0108-0400