SH7144_08 Datasheet, PDF (904/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

D. I/O Port Block Diagrams
RES
R
Q PE2DR D
C
PEDRL.WR
TIOC0C (MTU)
PEDRL.RD
TIOC0C (MTU)
DREQ1 (DMAC)
AUDRST (AUD)
PFC
Q PE2MD0
Q PE2MD1
Q PE2IOR
AUD module standby
Software standby
SBYCR
Q Hi-Z
RES: Reset signal
PEDRL.RD: Port E data register L read signal
PEDRL.WR: Port E data register L write signal
Figure D.48 PE2/TIOC0C/DREQ1/AUDRST
Symbol in Figure D.48
Available Products
SH7144
SH7145
Pins
Masked ROM
Masked ROM
version/
version/
F-ZTAT ROM less
PE2 TIOC0C DREQ1 AUDRST _{version version}
F-ZTAT ROM less
version version
PE2/TIOC0C/ PE2 TIOC0C DREQ1 AUDRST ⎯
⎯
DREQ1/
(MTU) (DMAC) (AUD)
AUDRST
√
⎯
Rev.4.00 Mar. 27, 2008 Page 860 of 882
REJ09B0108-0400