SH7144_08 Datasheet, PDF (447/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

13. Serial Communication Interface (SCI)
Bit Bit Name Initial Value R/W Description
5 TE
0
R/W Transmit Enable
When this bit is set to 1, transmission is enabled.
In this state, serial transmission is started when
transmit data is written to TDR and the TDRE flag in
SSR is cleared to 0.
SMR setting must be made to decide the transfer
format before setting the TE bit to 1. When this bit is
cleared to 0, transmit operation is disabled, and the
TDRE flag in SSR is fixed to 1.
4 RE
0
R/W Receive Enable
When this bit is set to 1, reception is enabled.
Serial reception is started in this state when a start
bit is detected in asynchronous mode or synchronous
clock input is detected in clocked synchronous mode.
SMR setting must be made to decide the receive
format before setting the RE bit to 1.
Clearing the RE bit to 0 disables reception and does
not affect the RDRF, FER, PER, and ORER flags,
which retain their states.
3 MPIE
0
R/W Multiprocessor Interrupt Enable (enabled only when
the MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and ORER status flags in SSR is
prohibited. On receiving data in which the
multiprocessor bit is 1, this bit is automatically
cleared and normal reception is resumed. For details,
refer to section 13.5, Multiprocessor Communication
Function.
When receive data including MPB = 0 is received,
receive data transfer from RSR to RDR, receive error
detection, and setting of the RDRF, FER, and ORER
flags in SSR, are not performed.
When receive data including MPB = 1 is received,
the MPB bit in SSR is set to 1, the MPIE bit is
cleared to 0 automatically, and generation of RXI and
ERI interrupts (when the TIE and RIE bits in SCR are
set to 1) and FER and ORER flag setting are
enabled.
Rev.4.00 Mar. 27, 2008 Page 403 of 882
REJ09B0108-0400