SH7144_08 Datasheet, PDF (78/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

2. CPU
Operation
Classification Types Code
Function
System
control
11
CLRT
T bit clear
CLRMAC MAC register clear
LDC
Load to control register
LDS
Load to system register
NOP
No operation
RTE
Return from exception processing
SETT
T bit set
SLEEP Transition to power-down mode
STC
Store control register data
STS
Store system register data
TRAPA Trap exception handling
Total:
62
No. of
Instructions
31
142
Rev.4.00 Mar. 27, 2008 Page 34 of 882
REJ09B0108-0400