SH7144_08 Datasheet, PDF (920/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

Main Revisions for this Edition
Item
Page Revision (See Manual for Details)
15.3.2 A/D Control/Status 545
Register_0, 1 (ADCSR_0,
ADCSR_1)
Table amended
Bit Bit Name Initial Value R/W Description
7 ADF
0
R/(W)* A/D End Flag
A status flag that indicates the end of A/D conversion.
[Setting conditions]
• When A/D conversion ends in single mode
• When A/D conversion ends on all specified
channels in scan mode
[Clearing conditions]
• When 0 is written after reading ADF = 1
• When the DMAC or the DTC is activated by an
ADI interrupt and data is read from ADDR while
the DTMR bit in the DTC is cleared to 0
16.2.2 Compare Match 561
Timer Control/Status
Register_0, 1 (CMCSR_0,
CMCSR_1)
Table amended
Bit Bit Name Initial Value R/W Description
7
CMF
0
R/(W)* Compare Match Flag
This flag indicates whether or not the CMCNT and
CMCOR values have matched.
0: CMCNT and CMCOR values have not matched
1: CMCNT and CMCOR values have matched
[Clearing condition]
• Write 0 to CMF after reading 1 from it
• When the DTC is activated by an CMI interrupt
and data is transferred with the DISEL bit in
DTMR of DTC = 0
19.1 Features
657 Description amended
• Reprogramming capability
See section 26.5, Flash Memory Characteristics.
19.8.3 Interrupt Handling 679
when
Programming/Erasing
Flash Memory
Figure 19.10
Erase/Erase-Verify
Flowchart
Figure amended
*1
Erase start
SWE bit ← 1
Wait (tSSWE) μs
n←1
Set EBR1 and EBR2
*3
19.11.3 Notes on Flash 683
Memory Programming and to
Erasing
685
23.5.7 Settings of AUD- 717
Related Pins when Using
E10A
Description replaced
Newly added
Rev.4.00 Mar. 27, 2008 Page 876 of 882
REJ09B0108-0400