SH7144_08 Datasheet, PDF (547/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
The following description gives the procedures for and operations of receiving data in one byte
units by fixing SCL low for every data reception using the HNDS bit function.
1. Clear the TRS bit in ICCR to 0 to change from the transmit mode to the receive mode.
Clear the ACKB bit in ICSR to 0 (setting of the acknowledge data).
Set the HNDS bit in SCRX to 1.
Clear the IRIC flag to 0 to confirm that reception has been completed.
When the first frame is the final receive data, perform end processing in step 6 and subsequent
steps.
2. When ICDR is read (a dummy read operation), the receiving of data starts; the receive clock is
output in synchronization with the internal clock, and the first datum is then received. (Data of
the SDA pin is stored in ICDRS in synchronization with the rising edge of receive clock.)
3. The master device sets SDA to low on the 9th cycle of the receive clock and returns the
acknowledge bit. The receive data is transferred from ICDRS to ICDRR at the rising edge of
the 9th cycle of the receive clock, and the ICDRF, IRIC, and IRTR flags are set to 1. When the
IEIC bit in ICCR has been set to 1, an interrupt request is generated for the CPU. The master
devise fixes SCL low between at the falling edge of 9th cycle of the receive clock and read of
ICDR data.
4. To identify the next interrupt, the IRIC flag is cleared to 0.
When the next frame is the final receive data, perform end processing in step 6 and subsequent
steps.
5. Read the receive data of ICDR. This clears the ICDRF flag to 0, and the master devise outputs
the receive clock continuously for the reception of the next data.
Data can be received by repeating the steps 3 to 5.
6. Set the ACKB bit to 1 (setting of acknowledge data for the final reception).
7. Read ICDR receive data. This clears the ICDRF flag to 0. The master device outputs the
receive clock to receive data.
8. When one frame of data has been received, the ICDRF, IRIC, and IRTR flags are set to 1 at the
rising edge of the 9th cycle of receive clock.
9. Clear the IRIC flag to 0.
10. Read ICDR receives data after setting the TRS bit to 1. This clears the ICDRF flag to 0.
11. Write 0 to BBSY and SCP in ICCR to generate the stop condition.
This changes SDA from low to high when SCL is high, and generates the stop condition.
Rev.4.00 Mar. 27, 2008 Page 503 of 882
REJ09B0108-0400