SH7144_08 Datasheet, PDF (709/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

19. Flash Memory (F-ZTAT Version)
19.5 Register Descriptions
The flash memory has the following registers. For details on register addresses and register states
during each processing, refer to section 25, List of Registers.
• Flash memory control register 1 (FLMCR1)
• Flash memory control register 2 (FLMCR2)
• Erase block register 1 (EBR1)
• Erase block register 2 (EBR2)
• RAM emulation register (RAMER)
19.5.1 Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is a register that makes the flash memory change to program mode, program-verify
mode, erase mode, or erase-verify mode. For details on register setting, refer to section 19.8, Flash
Memory Programming/Erasing.
Bit Bit Name Initial Value R/W Description
7
FEW
1/0
R
Flash Write Enable*
Reflects the input level at the FWP pin. It is set to 1
when a low level is input to the FWP pin, and cleared
to 0 when a high level is input.
6
SWE
0
R/W Software Write Enable
When this bit is set to 1 while the FEW bit is 1, flash
memory programming/erasing is enabled. When this
bit is cleared to 0, other FLMCR1 bits and all EBR1
and EBR2 bits cannot be set.
5
ESU
0
R/W Erase Setup
When this bit is set to 1 while the FEW and SWE bits
are 1, the flash memory changes to the erase setup
state. When it is cleared to 0, the erase setup state is
cancelled.
4
PSU
0
R/W Program Setup
When this bit is set to 1 while the FEW and SWE bits
are 1, the flash memory changes to the program
setup state. When it is cleared to 0, the program
setup state is cancelled.
Rev.4.00 Mar. 27, 2008 Page 665 of 882
REJ09B0108-0400