SH7144_08 Datasheet, PDF (270/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

11. Multi-Function Timer Pulse Unit (MTU)
11.3.3 Timer I/O Control Register (TIOR)
The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU
has eight TIOR registers, two each for channels 0, 3, and 4, and one each for channels 1 and 2.
Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is
valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM
mode 2, the output at the point at which the counter is cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
• TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4
Bit Bit Name Initial Value R/W Description
7 IOB3
0
R/W I/O Control B0 to B3
6 IOB2
0
R/W Specify the function of TGRB.
5 IOB1
0
R/W See the following tables.
4 IOB0
0
R/W TIORH_0: Table 11.10
TIOR_1: Table 11.12
TIOR_2: Table 11.13
TIORH_3: Table 11.14
TIORH_4: Table 11.16
3 IOA3
0
R/W I/O Control A0 to A3
2 IOA2
0
R/W Specify the function of TGRA.
1 IOA1
0
R/W See the following tables.
0 IOA0
0
R/W TIORH_0: Table 11.18
TIOR_1: Table 11.20
TIOR_2: Table 11.21
TIORH_3: Table 11.22
TIORH_4: Table 11.24
Rev.4.00 Mar. 27, 2008 Page 226 of 882
REJ09B0108-0400