SH7144_08 Datasheet, PDF (537/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
14.4 Operation
The I²C bus interface is capable of transferring data in either the serial format or the I²C bus
format.
14.4.1 I²C Bus Data Formats
The I²C bus format is referred to as an addressing format. The transfer of data in this addressing
format includes the transfer of acknowledge bits. This is shown in figure 14.3. The first frame
after the start condition always consists of nine bits.
The serial format is referred to as a ‘non-addressing format’. The transfer of data in this non-
addressing format does not include the transfer of an acknowledge bit. This is shown in figure
14.4. The I²C bus timing is shown in figure 14.5.
The symbols used in figures 14.3 to 14.5 are described in table 14.6.
(a) FS=0 or FSX=0
S
SLA
1
7
R/W A
1
1
1
DATA
n
A
1
m
A/A P
1
1
Number of bits
being transferred
(n=1 to 8)
Number of frames
being transferred
(m=1 or above)
(b) When the start condition is re-transmitted, FS=0 or FSX=0
S
SLA
R/W A
DATA
A/A S
1
7
11
n1
11
1
m1
SLA
R/W A
DATA
7
11
n2
A/A P
11
1
m2
Upper: Number of bits being transferred (n=1, n2=1 to 8)
Lower: Number of frames being transferred (m=1, m2=1 or above)
Figure 14.3 I²C Bus Data Format (I²C Bus Format)
FS=1 and FSX=1
S
DATA
1
8
1
DATA
n
m
P
1
Number of bits
being transferred
(n=1 to 8)
Number of frames
being transferred
(m=1 or above)
Figure 14.4 I²C Bus Data Format (Serial Format)
Rev.4.00 Mar. 27, 2008 Page 493 of 882
REJ09B0108-0400