SH7144_08 Datasheet, PDF (436/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

12. Watchdog Timer
12.6.7 Manual Reset in Watchdog Timer Mode
When an internal reset is effected by TCNT overflow in watchdog timer mode, the processor waits
until the end of the bus cycle at the time of manual reset generation before making the transition to
manual reset exception processing. Therefore, the bus cycle is retained in a manual reset, but if a
manual reset occurs while the bus is released, manual reset exception processing will be deferred
until the CPU acquires the bus. However, if the interval from generation of the manual reset until
the end of the bus cycle is equal to or longer than the internal manual reset interval of 512 cycles,
the internal manual reset source is ignored instead of being deferred, and manual reset exception
processing is not executed.
12.6.8 Note on Using WDTOVF Signal
Do not pull down the WDTOVF pin. If necessary, pull it down with resistance larger than 1 MΩ.
Rev.4.00 Mar. 27, 2008 Page 392 of 882
REJ09B0108-0400