SH7144_08 Datasheet, PDF (231/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

10. Direct Memory Access Controller (DMAC)
10.4.4 DMA Transfer Types
The DMAC supports the transfers shown in table 10.4. It can operate in the single address mode,
in which either the transfer source or destination is accessed using an acknowledge signal, or dual
access mode, in which both the transfer source and destination addresses are output. The dual
access mode consists of a direct address mode, in which the output address value is the object of a
direct data transfer, and an indirect address mode, in which the output address value is not the
object of the data transfer, but the value stored at the output address becomes the transfer object
address. The actual transfer operation timing varies with the bus mode. The DMAC has two bus
modes: cycle-steal mode and burst mode.
Table 10.4 Supported DMA Transfers
Destination
Source
Memory-
Mapped
External Device External External
with DACK
Memory Device
On-Chip
Memory
On-Chip
Peripheral
Module
External device with DACK Not available Single Single Not available Not available
External memory
Single
Dual
Dual
Dual
Dual
Memory-mapped external Single
device
Dual
Dual
Dual
Dual
On-chip memory
Not available Dual
Dual
Dual
Dual
On-chip peripheral module Not available Dual
Dual
Dual
Dual
Note: Dual address mode includes both direct address mode and indirect address mode.
Rev.4.00 Mar. 27, 2008 Page 187 of 882
REJ09B0108-0400