SH7144_08 Datasheet, PDF (218/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

10. Direct Memory Access Controller (DMAC)
Bit Bit Name Initial Value R/W
13 SM1
0
R/W
12 SM0
0
R/W
Description
Source Address Mode 1, 0
These bits specify increment/decrement of the DMA
transfer source address. These bit specifications are
ignored when transferring data from an external
device to address space in single address mode.
00: Source address fixed
01: Source address incremented (+1 during 8-bit
transfer, +2 during 16-bit transfer, +4 during 32-bit
transfer)
10: Source address decremented (–1 during 8-bit
transfer, –2 during 16-bit transfer, –4 during 32-
bit transfer)
11: Setting prohibited
When the transfer source is specified at an indirect
address, specify in source address register 3
(SAR_3) the actual storage address of the data you
want to transfer as the data storage address (indirect
address).
During indirect address mode, SAR_3 obeys the
SM1/SM0 setting for increment/decrement. In this
case, SAR_3’s increment/decrement is fixed at +4/–4
or 0, irrespective of the transfer data size specified
by TS1 and TS0.
Rev.4.00 Mar. 27, 2008 Page 174 of 882
REJ09B0108-0400