SH7144_08 Datasheet, PDF (45/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

Section 1 Overview
1. Overview
The SH7144 Group and SH7145 Group single-chip RISC (Reduced Instruction Set Computer)
microcomputers integrate a Renesas Technology original RISC CPU core with peripheral
functions required for system configuration.
The SH7144 Group and SH7145 Group CPU has a RISC-type instruction set. Most instructions
can be executed in one state (one system clock cycle), which greatly improves instruction
execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power.
With this CPU, it has become possible to assemble low cost, high performance/high-functioning
systems, even for applications that were previously impossible with microcomputers, such as real-
time control, which demands high speeds.
In addition, the SH7144 Group and SH7145 Group includes on-chip peripheral functions
necessary for system configuration, such as a direct memory access controller (DMAC), large-
capacity ROM and RAM, timers, a serial communication interface (SCI), an A/D converter, an
interrupt controller (INTC), and I/O ports. As an option, an I²C bus interface can also be
incorporated.
ROM and SRAM can be directly connected to the SH7144 Group and SH7145 Group MCU by
means of an external memory access support function. This greatly reduces system cost.
There are two versions of on-chip ROM: F-ZTAT^TM* (Flexible Zero Turn Around Time) that
includes flash memory, and masked ROM. The flash memory can be programmed with a
programmer that supports SH7144 Group and SH7145 Group programming, and can also be
programmed and erased by software. This enables LSI chip to be re-programmed at a user side
while mounted on a board.
Note: * F-ZTAT is a registered trademark of Renesas Technology Corp.
Rev.4.00 Mar. 27, 2008 Page 1 of 882
REJ09B0108-0400