SH7144_08 Datasheet, PDF (511/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
Section 14 I²C Bus Interface (IIC) Option
The I²C bus interface is an optional feature. When using this optional feature, pay attention to the
following point:
• A “W” is added to the product-type name of a mask-ROM product which includes an optional
feature.
This LSI incorporates a single-channel I²C bus interface. The I²C bus interface conforms to the
Philips I²C bus (Inter-IC bus) interface system and provides a subset of the functions. Note,
however, that the configuration of the registers that control the I²C bus differs on some points from
that of Phillips’.
Data transfer is carried out by the data line (SDA0) and clock line (SCL0). This makes the
interface efficient in terms of the use of area for connectors and printed circuits.
IFIIC60A_010020030800
Rev.4.00 Mar. 27, 2008 Page 467 of 882
REJ09B0108-0400