SH7144_08 Datasheet, PDF (170/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

8. Data Transfer Controller (DTC)
The 32-bit DTSAR designates the DTC transfer source address and the 32-bit DTDAR designates
the transfer destination address. After each transfer, DTSAR and DTDAR are independently
incremented, decremented, or left fixed depending on its register information.
Start
Initial settings
DTMR, DTCR, DTIAR, DTSAR, DTDAR
No
NMIF = AE = 0?
Yes
Transfer request
No
generated?
Yes
DTC vector read
Transfer information read
DTCRA = DTCRA – 1 (normal/block transfer mode)
DTCRAL = DTCRAL – 1 (repeat mode)
Transfer (1 transfer unit)
DTSAR, DTDAR update
DTCRB = DTCRB – 1 (block transfer mode)
NMIF • NMIM
No
+ AE = 1?
Yes
Transfer information write
Block
transfer mode and
Yes
DTCRB ≠ 0?
No
Transfer information write
NMI or address error
No
CHNE = 0?
Yes
CPU interrupt request
When DISEL = 1 or DTCRA = 0 (normal/block transfer mode)
When DISEL = 1 (repeat transfer mode)
End
Figure 8.5 DTC Operation Flowchart
Rev.4.00 Mar. 27, 2008 Page 126 of 882
REJ09B0108-0400