SH7144_08 Datasheet, PDF (566/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
When WAIT = 1, and FS = 0 or FSX = 0 (I²C bus format, wait inserted)
SCL
8
9
1
2
3
SDA
8
A
1
2
3
IRIC
User processing
IRIC clear
IRIC clear
(a) When data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception.
SCL
8
9
1
SDA
8
A
1
IRIC
User processing
IRIC clear
ICDR write (during transmission)
or ICDR read (during reception)
IRIC clear
(b) When data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception.
Figure 14.26 IRIC Flag Set Timing and the Control of SCL (2)
Rev.4.00 Mar. 27, 2008 Page 522 of 882
REJ09B0108-0400