SH7144_08 Datasheet, PDF (458/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

13. Serial Communication Interface (SCI)
Bit Bit Name Initial Value R/W Description
2
TEND 1
R Transmit End
This bit is set to 1 when no error signal has been sent
back from the receive side and the next transmit data is
ready to be transferred to TDR.
[Setting conditions]
• Power-on reset or software standby mode
• When the TE bit in SCR is 0 and the ESR bit is also 0
• When the ESR bit is 0 and the TDRE bit is 1 after the
specified interval following transmission of 1-byte data
The timing of bit setting differs according to the register
setting as follows:
When GM = 0 and BLK = 0, 2.5 etu after transmission
starts
When GM = 0 and BLK = 1, 1.0 etu after transmission
starts
When GM = 1 and BLK = 0, 1.5 etu after transmission
starts
When GM = 1 and BLK = 1, 1.0 etu after transmission
starts
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC is activated by a TXI interrupt
• When the DTC is activated by a TXI interrupt and
transmit data is transferred to TDR while the DISEL
bit in DTMR of the DTC is 0
1
MPB
0
R Multiprocessor
This bit is not used in smart card interface mode.
0
MPBT 0
R/W Multiprocessor Bit Transfer
Write 0 to this bit in smart card interface mode.
Note: * Only 0 can be written to clear the flag.
Rev.4.00 Mar. 27, 2008 Page 414 of 882
REJ09B0108-0400