SH7144_08 Datasheet, PDF (75/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

2. CPU
Instruction Formats
Source
Operand
Destination
Operand
Example
d format
15
xxxx xxxx
0
dddd dddd
d12 format
15
xxxx dddd
dddd
0
dddd
dddddddd: Indirect R0 (Direct register) MOV.L
GBR with
@(disp,GBR),R0
displacement
R0 (Direct register) dddddddd: Indirect MOV.L
GBR with
R0,@(disp,GBR)
displacement
dddddddd: PC
relative with
displacement
R0 (Direct register) MOVA
@(disp,PC),R0
—
dddddddd: PC
BF
label
relative
—
dddddddddddd: PC BRA label
relative
(label = disp
+ PC)
nd8 format
15
xxxx nnnn
dddd
0
dddd
dddddddd: PC
relative with
displacement
nnnn: Direct
register
MOV.L
@(disp,PC),Rn
i format
15
0
xxxx xxxx i i i i i i i i
iiiiiiii: Immediate
iiiiiiii: Immediate
Indirect indexed
GBR
AND.B
#imm,@(R0,GBR)
R0 (Direct register) AND #imm,R0
iiiiiiii: Immediate —
TRAPA #imm
ni format
15
0
xxxx nnnn i i i i i i i i
iiiiiiii: Immediate
nnnn: Direct
register
ADD #imm,Rn
Note: In multiply-and-accumulate instructions, nnnn is the source register.
Rev.4.00 Mar. 27, 2008 Page 31 of 882
REJ09B0108-0400