SH7144_08 Datasheet, PDF (758/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

23. Advanced User Debugger (AUD)
AUDCK
AUDSYNC
AUDATAn
0000 1000 A3 to A0
DIR
Input
Input/output changeover
A31 to A28
0000
Not ready
0001
Ready
0001 0001 D3 to D0 D7 to D4
Ready Ready
Output
Figure 23.5 Example of Read Operation (Byte Read)
AUDCK
AUDSYNC
AUDATAn
0000 1110 A3 to A0
DIR
Input/output changeover
A31 to A28 D3 to D0
D31 to D28
0000
Not ready
Input
0001
Ready
Output
0001 0001
Ready Ready
Figure 23.6 Example of Write Operation (Longword Write)
AUDCK
AUDSYNC
AUDATAn
0000 1010 A3 to A0
DIR
Input
Input/output changeover
A31 to A28
0000
Not ready
0101
Ready
(Bus error)
0101 0101
Ready Ready
(Bus error) (Bus error)
Output
Figure 23.7 Example of Error Occurrence (Longword Read)
Rev.4.00 Mar. 27, 2008 Page 714 of 882
REJ09B0108-0400