SH7144_08 Datasheet, PDF (556/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
Start condition generation
[7] SCL is fixed low until ICDR is read
SCL
(Pin waveform)
1
2
3
4
5
6
7
8
9
1
2
SCL
(Master output)
1
2
3
4
5
6
7
8
9
1
2
SCL
(Slave output)
SDA
(Master output)
SDA
(Slave output)
IRIC
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Slave address
R/W [6]
A
Interrupt
request
generation
bit 7 bit 6
Data 1
ICDRF
ICDRS
ICDRR
Undefined value
Address + R/W
Address + R/W
User processing [2] ICDR read
[8] IRIC clear
[10] ICDR read
(dummy read)
Figure 14.18 An Example of the Timing of Operations in Slave Receive Mode 1
(MLS = 0, HNDS = 1)
Rev.4.00 Mar. 27, 2008 Page 512 of 882
REJ09B0108-0400