SH7144_08 Datasheet, PDF (788/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

25. List of Registers
Register name
abbreviation NO. of bits Address
Module
Access size
NO. of Access states
I²C bus control register
I²C bus status register
⎯
ICCR
8
ICSR
8
⎯
⎯
H'FFFF8808
I²C
H'FFFF8809
[Option]
H'FFFF880A to
H'FFFF880D
8, 16
8
⎯
Pφ reference
B:2
W:4
I²C bus data register
ICDR
8
H'FFFF880E*
8, 16
Second slave address register
I²C bus mode register
SARX
8
ICMR
8
H'FFFF880E*
H'FFFF880F*
8, 16
8
Slave address register
SAR
8
H'FFFF880F*
8
⎯
⎯
⎯
H'FFFF8810 to ⎯
⎯
H'FFFF8A4F
Instruction register
SDIR
16
H'FFFF8A50
H-UDI
8, 16, 32
Pφ reference
Status register
Data register H
Data register L
SDSR
16
SDDRH
16
SDDRL
16
H'FFFF8A52
(Only in F-
8, 16
B:2
H'FFFF8A54
ZTAT version) _{8, 16, 32}
W:2
H'FFFF8A56
8, 16
L:4
⎯
⎯
H'FFFF8A58 to
⎯
H'FFFFBFFF
Note: * Registers that can be read from/written to differ according to the setting of the ICE bit in
the IIC bus control register 0. In ICE=0, the registers read from/written to are the second
slave address register 0 and the slave address register 0. In ICE=1, they are the IIC bus
data register 0 and the IIC bus mode register 0.
Rev.4.00 Mar. 27, 2008 Page 744 of 882
REJ09B0108-0400