SH7144_08 Datasheet, PDF (540/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
Note: The ICMR register should be modified after transmit/receive operation has been
completed. If the ICMR register is modified during transmit/receive operation, bit counter
BC2 to BC0 will be modified illegally, thus causing malfunction.
14.4.3 Operations in Master Transmission
In I²C bus format in the master transmit mode, the master device outputs the transmit clock and
data for transmission, and the slave device acknowledges its reception of data.
Figure 14.7 is a flowchart that gives an example of operations in master transmit mode.
Rev.4.00 Mar. 27, 2008 Page 496 of 882
REJ09B0108-0400