SH7144_08 Datasheet, PDF (742/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

22. User Debugging Interface (H-UDI)
22.3.2 Status Register (SDSR)
The status register (SDSR) is a 16-bit register that can be read and written to by the CPU. The
SDSR value can be output from TDO, but serial data cannot be written to SDSR via TDI. The
SDTRF bit is output by means of a one-bit shift. In a two-bit shift, the SDTRF bit is output first,
followed by a reserved bit.
SDSR is initialized by TRST signal input, but is not initialized in software standby mode.
Bit
Bit Name Initial value R/W Description
15 to 12 ⎯
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
11
⎯
1
R Reserved
This bit is always read as 1. The write value should
always be 1.
10 to 1 ⎯
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
0
SDTRF 1
R/W Serial Data Transfer Control Flag
Indicates whether H-UDI registers can be accessed by
the CPU. The SDTRF bit is initialized by the TRST
signal, but is not initialized in software standby mode.
0: Serial transfer to SDDR has ended, and SDDR can be
accessed
1: Serial transfer to SDDR is in progress
Rev.4.00 Mar. 27, 2008 Page 698 of 882
REJ09B0108-0400