SH7144_08 Datasheet, PDF (138/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

6. Interrupt Controller (INTC)
the IRQ status register (ISR). Interrupts held pending due to edge detection are cleared
by a power-on reset or a manual reset.
Program
execution state
Interrupt?
Yes
NMI?
Yes
No
No
No
User break?
Yes
IRQOUT = low
*1
H-UDI
No
interrupt?
Yes
Yes
Level 15
No
interrupt?
Yes
I3 to I0 ≤
level 14?
No
Yes
Level 14
interrupt?
Yes
I3 to I0 ≤
level 13?
No
Level 1
No
interrupt?
Yes
No
Yes
I3 to I0 =
level 0?
No
Save SR to stack
Save PC to stack
Copy accept-interrupt
level to I3 to I0
IRQOUT = high
*2
Read exception
vector table
Branch to exception
service routine
Notes: I3 to I0 are Interrupt mask bits of status register (SR) in the CPU
1. IRQOUT is the same signal as interrupt request signal to the CPU (see figure 6.1).
Therefore, IRQOUT is output when the request priority level is higher than the level in bits I3–I0 of SR.
2. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when
the CPU starts interrupt exception processing instead of instruction execution (namely, before saving SR to stack).
However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepted
and has output an interrupt request to the CPU, the IRQOUT pin holds low level.
Figure 6.3 Interrupt Sequence Flowchart
Rev.4.00 Mar. 27, 2008 Page 94 of 882
REJ09B0108-0400