SH7144_08 Datasheet, PDF (79/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

2. CPU
The table below shows the format of instruction codes, operation, and execution states. They are
described by using this format according to their classification.
• Instruction Code Format
Item
Format
Explanation
Instruction
Described in
mnemonic.
OP.Sz SRC,DEST
OP: Operation code
Sz: Size
SRC: Source
DEST: Destination
Rm: Source register
Rn: Destination register
imm: Immediate data
disp: Displacement*²
Instruction
code
Outline of the
Operation
Described in MSB ↔
LSB order
→, ←
(xx)
mmmm: Source register
nnnn: Destination register
0000: R0
0001: R1
⋅
⋅
⋅
1111: R15
iiii: Immediate data
dddd: Displacement
Direction of transfer
Memory operand
M/Q/T
Flag bits in the SR
&
Logical AND of each bit
|
Logical OR of each bit
^
Exclusive OR of each bit
~
Logical NOT of each bit
<<n
n-bit left shift
>>n
n-bit right shift
Execution
—
states
Value when no wait states are inserted*¹
T bit
—
Value of T bit after instruction is executed. An em-dash (—)
in the column means no change.
Notes: 1. Instruction execution states: The execution states shown in the table are minimums.
The actual number of states may be increased when (1) contention occurs between
instruction fetches and data access, or (2) when the destination register of the load
instruction (memory → register) equals to the register used by the next instruction.
2. Depending on the operand size, displacement is scaled by ×1, ×2, or ×4. For details,
refer the SH-1/SH-2/SH-DSP Software Manual.
Rev.4.00 Mar. 27, 2008 Page 35 of 882
REJ09B0108-0400