SH7144_08 Datasheet, PDF (572/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
14.5 Usage Notes
1. In master mode, when the instruction that generates the start condition is issued immediately
after the instruction that generates the stop condition, neither the start condition nor the stop
condition will be correctly output. For the consecutive output of the start condition and stop
condition, read the port after issuing the instruction that generates the start condition, and make
sure that the levels on both SCL and SDA are low. Then issue the instruction that generates the
stop condition. Note that SCL may not have completely reached its low level when BBSY
becomes 1.
2. The following two conditions apply to the start of the next transfer: take note when reading
from/writing to ICDR.
⎯ ICE = 1, TRS = 1, and data is written to ICDR (including automatic transfer from ICDRT
to ICDRS)
⎯ ICE = 1, TRS = 0, and data is read from ICDR (including automatic transfer from ICDRS
to ICDRR)
3. In synchronization with the internal clock, SCL and SDA are output with the timing shown in
table 14.8. The timing on the bus is determined by the rise/fall times of the signals, and these
are affected by the bus-load’s capacitance, series resistance, and parallel resistance.
Table 14.8 I²C Bus Timing (output of SCL and SDA)
Item
Symbol Output Timing Unit
SCL-output cycle time
SCL-output high-pulse width
SCL-output low-pulse width
SDA-output bus-free time
Start-condition-output hold time
Output setup time for re-transmission of start
condition
t
SCLO
t_SCLHO
t_SCLLO
t
BUFO
t
STAHO
t
STASO
28 t to 256 t
ns
pcyc
pcyc
0.5 t_SCLO
ns
0.5 t_SCLO
ns
0.5 t −1 t
ns
SCLO
pcyc
0.5 t −1 t
ns
SCLO
pcyc
1t
ns
SCLO
Setup time for output of the stop condition
t_STOSO
0.5 t_SCLO +2 t_pcyc
ns
Setup time for the output of data (master)
t_SDASO
1 t_SCLLO −3 t_pcyc
ns
Setup time for the output of data (slave)
1 t_SCLL −(6 t_pcyc or 12 ns
t_pcyc *)
Data-output hold time
t_SDAHO
3 t_pcyc
ns
Note:
*
When the IICX is 0, 6 t . When IICX is 1, 12 t .
pcyc
pcyc
Remarks
Rev.4.00 Mar. 27, 2008 Page 528 of 882
REJ09B0108-0400