SH7144_08 Datasheet, PDF (729/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

19. Flash Memory (F-ZTAT Version)
Apply the reset signal while SWE is low to reset the flash memory during its operation: The
reset signal is applied at least 100 μs after the SWE bit has been cleard.
Comply with power-on procedure designated by the programmer maker: When executing an
on-board writing with a programmer, incorrect programming or erasing may occur unless the
power-on procedure designated by the programmer makers is applied.
CK
Vcc
FWP
Wait time: tsswe
Programmable/
erasable
Wait time: 100μs
tOSC1
tMDS*³
min 0μs
min 0μs
MD3 to MD0*¹
RES
SWE bit
tMDS*³
SWE set
SWE clear
Prohibition time of accessing flash memory
(tsswe : Wait time after SWE set)*²
Reprogrammable time of flash memory
(Prohibition of program execution on flash memory and of reading data except verify)
Notes: 1. Levels of mode pins (MD3 to MD0) should be fixed to pull down or pull up until power-off except mode
switchimg occasion.
2. See section 26.5, Flash Memory Characteristics.
3. See section 26.3.3, Control Signal Timing.
Figure 19.11 Power On/Off Timing (Boot Mode)
Rev.4.00 Mar. 27, 2008 Page 685 of 882
REJ09B0108-0400