SH7144_08 Datasheet, PDF (567/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

When FS = 1 and FSX = 1 (synchronous serial format)
SCL
7
8
1
14. I²C Bus Interface (IIC) Option
2
3
4
SDA
7
8
1
2
3
4
IRIC
User processing
IRIC clear
(a) When data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception.
SCL
7
8
1
SDA
7
8
1
IRIC
User processing
IRIC clear
ICDR write (during transmission) _{IRIC clear}
or ICDR read (during reception)
(b) When data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception.
Figure 14.27 IRIC Flag Set Timing and the Control of SCL (3)
Rev.4.00 Mar. 27, 2008 Page 523 of 882
REJ09B0108-0400