SH7144_08 Datasheet, PDF (204/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

9. Bus State Controller (BSC)
9.7.2 Simplification of Bus Cycle Start Detection
For consecutive accesses to the same CS space, waits are inserted to provide the number of idle
cycles designated by bits CW3 to CW0 in BCR2. However, in the case of a write cycle after a
read, the number of idle cycles inserted will be the larger of the two values designated by the IW
and CW bits. When idle cycles already exist between access cycles, waits are not inserted.
Figure 9.8 shows an example. A continuous access idle is specified for CSn space, and CSn space
is consecutively write-accessed.
CK
Address
CSn
RD
WRxx
Data
T1
T2
Tidle
T1
T2
CSn space access Idle cycle CSn space access
Figure 9.8 Example of Idle Cycle Insertion at Same Space Consecutive Access
Rev.4.00 Mar. 27, 2008 Page 160 of 882
REJ09B0108-0400