SH7144_08 Datasheet, PDF(432/930 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

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SH7144_08 Datasheet, PDF (432/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

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12. Watchdog Timer

12.4.5 Timing of Setting Watchdog Timer Overflow Flag (WOVF)

When TCNT overflows in watchdog timer mode, the WOVF bit of RSTCSR is set to 1 and a

WDTOVF signal is output. When the RSTE bit in RSTCSR is set to 1, TCNT overflow enables an

internal reset signal to be generated for the entire chip. Figure 12.5 shows this timing.

Ï

TCNT

Overflow signal

(internal signal)

H'FF H'00

WOVF

Figure 12.5 Timing of Setting WOVF

12.5 Interrupt Source

During interval timer mode operation, an overflow generates an interval timer interrupt (ITI). The

interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be

cleared to 0 in the interrupt handling routine.

Table 12.2 WDT Interrupt Source (in Interval Timer Mode)

Name

ITI

Interrupt Source

TCNT overflow

Interrupt Flag

OVF

DMAC/DTC Activation

Impossible

Rev.4.00 Mar. 27, 2008 Page 388 of 882

REJ09B0108-0400

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