SH7144_08 Datasheet, PDF (311/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

11. Multi-Function Timer Pulse Unit (MTU)
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 11.13.
Compare match signal
Buffer
register
Timer general
register
Comparator
TCNT
Figure 11.13 Compare Match Buffer Operation
• When TGR is an input capture register
When input capture occurs, the value in TCNT is transferred to TGR and the value previously
held in the timer general register is transferred to the buffer register.
This operation is illustrated in figure 11.14.
Input capture
signal
Buffer
register
Timer general
register
TCNT
Figure 11.14 Input Capture Buffer Operation
Example of Buffer Operation Setting Procedure: Figure 11.15 shows an example of the buffer
operation setting procedure.
Buffer operation
Select TGR function
[1]
Set buffer operation
[2]
[1] Designate TGR as an input capture register or
output compare register by means of TIOR.
[2] Designate TGR for buffer operation with bits
BFA and BFB in TMDR.
[3] Set the CST bit in TSTR to 1 start the count
operation.
Start count
[3]
<Buffer operation>
Figure 11.15 Example of Buffer Operation Setting Procedure
Rev.4.00 Mar. 27, 2008 Page 267 of 882
REJ09B0108-0400