SH7144_08 Datasheet, PDF (766/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

24. Power-Down Modes
24.2.1 Standby Control Register (SBYCR)
SBYCR is an 8-bit readable/writable register that performs software standby mode control.
Bit Bit Name Initial Value R/W
7
SSBY
0
R/W
6
Hi-Z
0
R/W
5
—
0
R
4 to 2 —
All 1
R
Description
Software Standby
This bit specifies the transition mode after executing
the SLEEP instruction.
0: Shifts to sleep mode after the SLEEP instruction
has been executed
1: Shifts to software standby mode after the SLEEP
instruction has been executed
This bit cannot be set to 1 when the watchdog timer
(WDT) is operating (when the TME bit in TCSR of
the WDT is set to 1). When transferring to software
standby mode, clear the TME bit to 0, stop the WDT,
then set the SSBY bit to 1.
Port High-Impedance
In software standby mode, this bit selects whether
the pin state of the I/O port is retained or changed to
high-impedance.
0: In software standby mode, the pin state is retained.
1: In software standby mode, the pin state is changed
to high-impedance.
The HIZ bit cannot be set to 1 when the TME bit in
TCSR of the WDT is set to 1.
When changing the pin state of the I/O port to high-
impedance, clear the TME bit to 0, then set the HIZ
bit to 1.
Reserved
This bit is always read as 0, and should always be
written with 0.
Reserved
These bits are always read as 1, and should always
be written with 1.
Rev.4.00 Mar. 27, 2008 Page 722 of 882
REJ09B0108-0400