SH7144_08 Datasheet, PDF (579/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
9. Points for caution in the execution of the instruction that sets the I²C bus interface stop
condition
If the rise time in the 9th cycle of SCL exceeds the specified value due to a high bus-load
capacitance, or if a slave device inserts a wait by setting the level on SCL low, read SCL after
the rise of 9th cycle of the clock to confirm that the level is low, and then execute the
instruction that sets the stop condition.
SCL
SDA
9^th cycle
VIH
Period for securing
the high-level period
SCL is detected as low
since this waveform takes
a long time to rise.
IRIC
Stop condition
[1] Decision on whether [2] Stop condition instruction
or not SCL is low
generation
Figure 14.31 Timing for the Setting of the Stop Condition
10. Notes on WAIT function
⎯ Conditions to cause this phenomenon
When both of the following conditions are satisfied, the clock pulse of the 9th clock could
be outputted continuously in master mode using the WAIT function due to the failure of
the WAIT insertion after the 8th clock fall.
(1) Setting the WAIT bit of the ICMR register to 1 and operating WAIT, in master mode
(2) If the IRIC bit of interrupt flag is cleared from 1 to 0 between the fall of the 7th clock
and the fall of the 8th clock.
⎯ Error phenomenon
Normally, WAIT State will be cancelled by clearing the IRIC flag bit from 1 to 0 after the
fall of the 8th clock in WAIT State. In this case, if the IRIC flag bit is cleared between the
7th clock fall and the 8th clock fall, the IRIC flag clear- data will be retained internally.
Therefore, the WAIT State will be cancelled right after WAIT insertion on 8th clock fall.
⎯ Restrictions
Please clear the IRIC flag before the rise of the 7th clock (the counter value of BC2
through BC0 should be 2 or greater), after the IRIC flag is set to 1 on the rise of the 9th
clock.
Rev.4.00 Mar. 27, 2008 Page 535 of 882
REJ09B0108-0400