SH7144_08 Datasheet, PDF (455/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

13. Serial Communication Interface (SCI)
• Smart card interface mode (when SMIF in SDCR is 1)
Bit Bit Name Initial Value R/W Description
7
TDRE 1
R/(W)* Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
• Power-on reset or software standby mode
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC is activated by a TXI interrupt
• When the DTC is activated by a TXI interrupt and
transmit data is transferred to TDR while the
DISEL bit in DTMR of the DTC is 0
6
RDRF 0
R/(W)* Receive Data Register Full
Indicates that the receive data is stored in RDR.
[Setting condition]
• When serial reception ends normally and receive
data is transferred from RSR to RDR
[Clearing conditions]
• Power-on reset or software standby mode
• When 0 is written to RDRF after reading RDRF =
1
• When the DMAC is activated by an RXI interrupt
• When the DTC is activated by an RXI interrupt
and data is transferred from RDR while the DISEL
bit in DTMR of the DTC is 0
The RDRF flag is not affected and retains its previous
value even if the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the
RDRF flag is still set to 1, an overrun error will occur
and the receive data will be lost.
Rev.4.00 Mar. 27, 2008 Page 411 of 882
REJ09B0108-0400