SH7144_08 Datasheet, PDF (178/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

8. Data Transfer Controller (DTC)
8.4 Procedures for Using DTC
8.4.1 Activation by Interrupt
The procedure for using the DTC with interrupt activation is as follows:
1. Set the DTMR, DTCRA, DTSAR, DTDAR, DTCRB, and DTIAR register information in
memory space.
2. Specify the register information start address with DTBR and the DTC vector table.
3. Set the corresponding DTER bit to 1.
4. The DTC is activated when an interrupt source occurs.
5. When interrupt requests are not made to the CPU, the interrupt source is cleared, but the DTER
is not. When interrupts are requested, the interrupt source is not cleared, but the DTER is.
6. Interrupt sources are cleared within the CPU interrupt routine. When doing continuous DTC
data transfers, set the DTER to 1 after reading DTER = 0.
8.4.2 Activation by Software
The procedure for using the DTC with software activation is as follows:
1. Set the DTMR, DTCRA, DTSAR, DTDAR, DTCRB, and DTIAR register information in
memory space.
2. Set the start address of the register information in the DTBR register and the DTC vector
address.
3. Check that the SWDTE bit is 0.
4. Write 1 to SWDTE bit and the vector number to DTVEC.
5. Check the vector number written to DTVEC.
6. After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested,
the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit
to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the
SWDTE bit is held at 1 and a CPU interrupt is requested.
7. The SWDTE bit is cleared to 0 within the CPU interrupt routine. For continuous DTC data
transfer, set the SWDTE bit to 1 after confirming that its current value is 0. Then write the
vector number to DTVEC for continuous DTC transfer.
Rev.4.00 Mar. 27, 2008 Page 134 of 882
REJ09B0108-0400