SH7144_08 Datasheet, PDF (419/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

11. Multi-Function Timer Pulse Unit (MTU)
Bit Bit Name Initial value R/W Description
8 OIE
0
R/W Output Short Interrupt Enable
This bit makes interrupt requests when the OSF bit
of the OCSR is set.
00: Interrupt requests disabled
01: Interrupt request enabled
7 to 0 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Note: * Only 0 can be written to write the flag.
11.9.4 Operation
Input Level Detection Operation:
If the input conditions set by the ICSR1 occur on any of the POE pins, all high-current pins
become high-impedance state. Note however, that these high-current pins become high-impedance
state only when general input/output function or MTU function is selected in these pins.
1. Falling Edge Detection
When a change from high to low level is input to the POE pins.
2. Low-Level Detection
Figure 11.115 shows the low-level detection operation. Sixteen continuous low levels are
sampled with the sampling clock established by the ICSR1. If even one high level is detected
during this interval, the low level is not accepted.
Sampling starts when detecting the falling edge of the POE pin. Thereby, negate the POE pin
when using POE function after sampling.
Furthermore, the timing when the large-current pins enter the high-impedance state from the
sampling clock is the same in both falling-edge detection and in low-level detection.
Rev.4.00 Mar. 27, 2008 Page 375 of 882
REJ09B0108-0400