SH7144_08 Datasheet, PDF (364/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

11. Multi-Function Timer Pulse Unit (MTU)
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC/DMAC is activated, the flag is cleared automatically. Figure 11.68 shows
the timing for status flag clearing by the CPU, and figure 11.69 shows the timing for status flag
clearing by the DTC/DMAC.
TSR write cycle
T1
T2
Pφ
Address
TSR address
Write signal
Status flag
Interrupt
request signal
Figure 11.68 Timing for Status Flag Clearing by CPU
Pφ
Address
DTC/DMAC
read cycle
T1
T2
DTC/DMAC
write cycle
T1
T2
Source address
Destination
address
Status flag
Interrupt
request signal
Figure 11.69 Timing for Status Flag Clearing by DTC/DMAC Activation
Rev.4.00 Mar. 27, 2008 Page 320 of 882
REJ09B0108-0400