SH7144_08 Datasheet, PDF (551/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
The following description gives the procedures to receive data serially in synchronization with
ICDR (ICDRR) reading operation using wait operation (WAIT bit). The following description
gives the procedures to receive multiple bytes. For the operation of receiving only one byte, see
the flowchart in figure 14.14, since some procedures are omitted in the following description.
1. Clear the TRS bit in ICCR to 0 to change from the transmit mode to the receive mode.
Clear the ACKB bit in ICSR to 0 (setting of the acknowledge data).
Clear the HNDS bit in SCRX to 0 (canceling of the hand-shake function).
Clear the IRIC flag to 0, and then set the WAIT bit to 1.
2. When ICDR is read (a dummy read operation), the receiving of data starts; the receive clock is
output in synchronization with the internal clock, and the first datum is then received.
3. The IRIC flag is set to 1 according to the following two. In this case, if the IEIC bit in ICCR is
set to 1, an interrupt request is generated to the CPU.
A. The IRIC flag is set to 1 at the falling edge of the 8th cycle of one frame of the receive
clock.
The SCL is automatically fixed low in synchronization with the internal clock until the
IRIC flag is cleared.
B. The IRIC flag is set to 1 at the rising edge of the 9th cycle of one frame of the receive
clock.
The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been
completely received. The master device continues outputting the receive clock for the next
receive data.
4. Read the IRTR flag in ICSR.
When the IRTR flag is 0, cancel the wait operation by clearing the IRIC flag as described in
step 6.
When the IRTR flag is 1 and the next data to be received is the final data, perform the end
operation described in step 7.
5. When the IRTR flag is 1, read the receive data in ICDR.
6. Clear the IRIC flag to 0. In the case of step 3 A, the master devise outputs the 9th cycle of the
receive clock, drives the SDA to low, and returns acknowledgement.
Data can be received by repeating steps 3 to 6.
7. Set the ACKB bit in ICSR to 1 and set the acknowledge data for the final reception.
8. Wait for at least one cycle of clock and the first cycle of the next receive data rises since the
IRIC flag is set to 1.
9. Change the mode from receive to transmit by setting the TRS bit in ICCR to 1. The set value
of the TRS bit becomes valid after the rising edge of the 9th cycle of the clock is input.
10. Read the receive data in ICDR.
Rev.4.00 Mar. 27, 2008 Page 507 of 882
REJ09B0108-0400