SH7144_08 Datasheet, PDF (497/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

13. Serial Communication Interface (SCI)
bits in SDCR to 0. According to smart card regulations, clear the O/E bit in SMR to 0 to select
even parity mode.
(Z) A Z Z A A A A A A Z
Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp
(Z) State
Figure 13.24 Inverse Convention (DIR = SINV = O/E = 1)
With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to
state Z, and transfer is performed in MSB-first order. The above start character data is H'3F. For
the inverse convention type, set the DIR and SINV bits in SDCR to 1. According to smart card
regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to state Z. In
this LSI, the SINV bit inverts only data bits D0 to D7. Therefore, set the O/E bit in SMR to 1 to
invert the parity bit for both transmission and reception.
13.7.3 Block Transfer Mode
Operation in block transfer mode is the same as that in the normal smart card interface mode,
except for the following points.
• In reception, though the parity check is performed, no error signal is output even if an error is
detected. However, the PER bit in SSR is set to 1 and must be cleared before receiving the
parity bit of the next frame.
• In transmission, a guard time of at least 1 etu is left between the end of the parity bit and the
start of the next frame.
• In transmission, because retransmission is not performed, the TEND flag is set to 1, 11.5 etu
after transmission start.
• As with the normal smart card interface, the ERS flag indicates the error signal status, but
since error signal transfer is not performed, this flag is always cleared to 0.
Rev.4.00 Mar. 27, 2008 Page 453 of 882
REJ09B0108-0400