SH7144_08 Datasheet, PDF (237/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

10. Direct Memory Access Controller (DMAC)
CK
A21–A0
CSn
D15–D0
Internal
address
bus
Internal
data bus
DMAC
indirect
address
buffer
DMAC
data
buffer
RD
WRH,
WRL
Transfer
source
address (H)
Transfer
source
address (L)
NOP
Indirect
address
Transfer
destination
address
Indirect
address (H)
Indirect
address (L)
Transfer source
address ∗¹
NOP
Indirect address ∗²
Transfer
data
Transfer
data
Indirect
address
Transfer
data
Transfer
data
Indirect
address
Transfer
data
Address read cycle
(1st)
(2nd)
NOP
cycle
Data
read cycle
(3rd)
Data
write cycle
(4th)
Notes: 1. The internal address bus is controlled by the port and does not change.
2. DMAC does not fetch value until 32-bit data is read from the internal data
bus.
Figure 10.9 Dual Address Mode and Indirect Address Transfer Timing Example
(External Memory Space to External Memory Space, 16-Bit Width)
Rev.4.00 Mar. 27, 2008 Page 193 of 882
REJ09B0108-0400