SH7144_08 Datasheet, PDF (531/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
Bit Bit Name Initial Value R/W Description
4 AASX 0
R/(W)* Second Slave Address Detection Flag
In the I²C bus format in the slave mode, this bit indicates that
the first frame after the start condition matches bits SVAX6 to
SVAX0 in SARX.
[Setting condition]
• Detection of the second slave address in the slave receive
mode while FSX = 0.
[Clearing conditions]
• Writing of 0 to this bit after reading AASX = 1
• Detection of the start condition.
• Entering master mode
3 AL
0
R/(W)* Arbitration Lost Flag
The AL flag indicates that the device, in master mode, has
failed to acquire bus-master status.
[Setting conditions]
• When the interface is in master transmit mode, the SDA
value it is generating internally and the value on the SDA
pin do not match on the rising edge of SCL.
• When the start condition instruction has been executed in
master transmit mode, then the SDA is driven to low by
another device before drives the pin to low.
[Clearing conditions]
• Writing of data to ICDR (during transmission) or reading of
data from ICDR (during reception).
• Writing a 0 to this bit after reading it as 1
Rev.4.00 Mar. 27, 2008 Page 487 of 882
REJ09B0108-0400