SH7144_08 Datasheet, PDF (513/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
Figure 14.1 is a block diagram of the I²C bus interface. Figure 14.2 shows an example of the
connection of I²C bus interfaces. Since the I/O pins are driven only by the NMOS transistor, they
operate in the same way as pins driven by an open-drain NMOS transistor. The voltage that can be
applied to the I/O pins depends on the supply voltage of the LSI.
SCRX
Pφ
PS
SCL
Noise
canceller
SDA
Noise
canceller
Clock
control
Bus state
detection circuit
Arbitration
detection circuit
Output data
control cricuit
ICCR
ICMR
ICSR
ICDRT
ICDRS
ICDRR
Address comparater
SAR, SARX
[Legend]
ICCR:
ICMR:
ICSR:
ICDR:
SCRX:
SAR:
SARX:
PS:
I²C control register
I²C mode register
I²C status register
I²C data register
Serial control register X
Slave address register
Slave address register X
Prescaler
Interrupt
generation
circuit
Interrupt request
Figure 14.1 A Block Diagram of the I²C Bus Interface
Rev.4.00 Mar. 27, 2008 Page 469 of 882
REJ09B0108-0400