SH7144_08 Datasheet, PDF (291/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

11. Multi-Function Timer Pulse Unit (MTU)
Bit Bit Name Initial Value R/W Description
3
TGFD
0
R/(W)* Input Capture/Output Compare Flag D
Status flag that indicates the occurrence of TGRD input
capture or compare match in channels 0, 3, and 4. Only
0 can be written, for flag clearing. In channels 1 and 2,
bit 3 is reserved. It is always read as 0 and the write
value should always be 0.
[Setting conditions]
• When TCNT = TGRD and TGRD is functioning as
output compare register
• When TCNT value is transferred to TGRD by input
capture signal and TGRD is functioning as input
capture register
[Clearing conditions]
• When DTC is activated by TGID interrupt and the
DISEL bit of DTMR in DTC is 0
• When 0 is written to TGFD after reading TGFD = 1
2
TGFC
0
R/(W)* Input Capture/Output Compare Flag C
Status flag that indicates the occurrence of TGRC input
capture or compare match in channels 0, 3, and 4. Only
0 can be written, for flag clearing. In channels 1 and 2,
bit 2 is reserved. It is always read as 0 and the write
value should always be 0.
[Setting conditions]
• When TCNT = TGRC and TGRC is functioning as
output compare register
• When TCNT value is transferred to TGRC by input
capture signal and TGRC is functioning as input
capture register
[Clearing conditions]
• When DTC is activated by TGIC interrupt and the
DISEL bit of DTMR in DTC is 0
• When 0 is written to TGFC after reading TGFC = 1
Rev.4.00 Mar. 27, 2008 Page 247 of 882
REJ09B0108-0400