SH7144_08 Datasheet, PDF (580/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
If the IRIC flag-clear is delayed due to the interrupt or other processes and the value of BC
counter is turned to 1 or 0, please confirm the SCL pins are in L’ state after the counter
value of BC2 through BC0 is turned to 0, and clear the IRIC flag. (See figure 14.32.)
ASD
SCL
A
Transmit/receive data
A
Transmit/receive
data
SCL =
9 1 2 3 4 5 6 7 8 _{‘L’ confirm} 9 1 2 3
BC2–BC0
0
IRIC
(operation
example)
7 6 5 4 3 21
IRIC flag clear available
0
7
IRIC clear
65
When BC2-0 ≥ 2
IRIC clear
IRIC flag clear available
IRIC flag clear unavailable
Figure 14.32 IRIC Flag Clear Timing on WAIT Operation
11. Points for caution of clearing the IRIC flag when the wait function is used
While the wait function is used in I²C bus interface master mode, if the rise time of SCL
exceeds the specified value or if a slave device in which a wait can be inserted by driving SCL
low is used, read SCL in the following way to confirm that SCL has become low, and then
clear the IRIC flag.
If the IRIC flag is cleared to 0 with WAIT = 1 while SCL is extending the high level period,
the SDA level may change before SCL becomes low, generate a start or stop condition
erroneously.
SCL
SDA
Secure period in which SCL is high
VIH
SCL is detected as low
IRIC
[1] Decision on whether or not [2] IRIC clear
SCL is low
Figure 14.33 Timing for Clearing IRIC Flag When WAIT = 1
Rev.4.00 Mar. 27, 2008 Page 536 of 882
REJ09B0108-0400