SH7144_08 Datasheet, PDF (427/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

12. Watchdog Timer
Bit Bit Name Initial Value R/W Description
4, 3 —
All 1
R
Reserved
These bits are always read as 1. The write value
should always be 1.
2 CKS2
0
R/W Clock Select 2 to 0
1 CKS1
0
0 CKS0
0
R/W Select one of eight internal clock sources for input to
R/W
TCNT. The clock signals are obtained by dividing
the frequency of the system clock (φ). The overflow
frequency for φ = 40 MHz is enclosed in
parentheses*².
000: Clock φ/2 (overflow interval: 12.8 μs)
001: Clock φ/64 (overflow interval: 409.6 μs)
010: Clock φ/128 (overflow interval: 0.8 ms)
011: Clock φ/256 (overflow interval: 1.6 ms)
100: Clock φ/512 (overflow interval: 3.3 ms)
101: Clock φ/1024 (overflow interval: 6.6 ms)
110: Clock φ/4096 (overflow interval: 26.2 ms)
111: Clock φ/8192 (overflow interval: 52.4 ms)
Notes: 1. Only a 0 can be written after reading 1.
2. The overflow interval listed is the time from when the TCNT begins counting at H'00
until an overflow occurs.
Rev.4.00 Mar. 27, 2008 Page 383 of 882
REJ09B0108-0400