SH7144_08 Datasheet, PDF (696/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

18. I/O Ports
18.5.2 Port E Data Register L (PEDRL)
The port E data register L (PEDRL) is a 16-bit readable/writable registers that stores port E data.
Bits PE15DR to PE0DR correspond to pins PE15 to PE0 (multiplexed functions omitted here).
When a pin functions is a general output, if a value is written to PEDRL, that value is output
directly from the pin, and if PEDRL is read, the register value is returned directly regardless of the
pin state.
When a pin functions is a general input, if PEDRL is read, the pin state, not the register value, is
returned directly. If a value is written to PEDRL, although that value is written into PEDRL it
does not affect the pin state. Table 18.5 summarizes port E data register read/write operations.
• PEDRL
Bit Bit Name Initial Value R/W
15 PE15DR 0
R/W
14 PE14DR 0
R/W
13 PE13DR 0
R/W
12 PE12DR 0
R/W
11 PE11DR 0
R/W
10 PE10DR 0
R/W
9 PE9DR 0
R/W
8 PE8DR 0
R/W
7 PE7DR 0
R/W
6 PE6DR 0
R/W
5 PE5DR 0
R/W
4 PE4DR 0
R/W
3 PE3DR 0
R/W
2 PE2DR 0
R/W
1 PE1DR 0
R/W
0 PE0DR 0
R/W
Description
See table 18.5
Rev.4.00 Mar. 27, 2008 Page 652 of 882
REJ09B0108-0400