SH7144_08 Datasheet, PDF (177/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

8. Data Transfer Controller (DTC)
8.3.6 DTC Execution State Counts
Table 8.5 shows the execution state for one DTC data transfer. Furthermore, table 8.6 shows the
state counts needed for execution state.
Table 8.5 Execution State of DTC
Mode
Register
Information
Vector Read I Read/Write J Data Read K
Normal
1
7
1
Repeat
1
7
1
Block transfer 1
7
N
N: block size (default set values of DTCRB)
Data Write L
1
1
N
Internal
Operation M
1
1
1
Table 8.6 State Counts Needed for Execution State
Access Objective
On-chip On-chip Internal I/O
RAM ROM Register
Bus width
Access state
32
32
8 or 16
1
1
2*¹
3*²
Execution Vector read
S_I
—
state
Register information S
1
J
read/write
1
——
1
——
Byte data read
S
1
K
1
2
3
Word data read
S
1
K
1
2
3
Long word data read S_K
1
1
4
6
Byte data write
S_L
1
1
2
3
Word data write
S_L
1
1
2
3
Longword data write S_L
1
1
4
6
Internal operation
S_M
1
Notes: 1. Two state access module: port, INT, CMT, SCI, etc.
2. Three state access module: WDT, UBC, etc.
External Device
8
16 32
2
2
2
4
2
2
8
4
2
2
2
2
4
2
2
8
4
2
2
2
2
4
2
2
8
4
2
The execution state count is calculated using the following formula. Σ indicates the number of
transfers by one activating source (count + 1 when CHNE bit is set to 1).
Execution state count = I · S + Σ (J · S + K · S + L · S ) + M · S
I
J
K
L
M
Rev.4.00 Mar. 27, 2008 Page 133 of 882
REJ09B0108-0400