HD64F2168 Datasheet, PDF (97/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Bit Bit Name Initial Value
4 IICE
0
3 FLSHE
0
2—
0
1 ICKS1
0
0 ICKS0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
IIC Master Enable
Enables or disables CPU access for IIC registers
(ICCR, ICSR, ICDR/SARX, ICMR/SAR), PWMX
registers (DADRAH/DACR, DADRAL,
DADRBH/DACNTH, DADRBL/DACNTL), and SCI
registers (SMR, BRR, SCMR).
0: SCI_1 registers are accessed in an area from
H'FFFF88 to H'FFFF89 and from H'FFFF8E to
H'FFFF8F.
SCI_2 registers are accessed in an area from
H'FFFFA0 to H'FFFFA1 and from H'FFFFA6 to
H'FFFFA7.
SCI_0 registers are accessed in an area from
H'FFFFD8 to H'FFFFD9 and from H'FFFFDE to
H'FFFFDF.
1: IIC_1 registers are accessed in an area from
H'FFFF88 to H'FFFF89 and from H'FFFF8E to
H'FFFF8F.
PWMX registers are accessed in an area from
H'FFFFA0 to H'FFFFA1 and from H'FFFFA6 to
H'FFFFA7.
IIC_0 registers are accessed in an area from
H'FFFFD8 to H'FFFFD9 and from H'FFFFDE to
H'FFFFDF.
Flash Memory Control Register Enable
Enables or disables CPU access for flash memory
registers (FCCS, FPCS, FECS, FKEY, FMATS,
FTDAR), control registers of power-down states
(SBYCR, LPWRCR, MSTPCRH, MSTPCRL), and
control registers of on-chip peripheral modules
(BCR2, WSCR2, PCSR, SYSCR2).
0: Area from H'FFFE88 to H'FFFE8F is reserved.
Control registers of power-down states and on-
chip peripheral modules are accessed in an area
from H'FFFF80 to H'FFFF87.
1: Control registers of flash memory are accessed in
an area from H'FFFE88 to H'FFFE8F.
Area from H'FFFF80 to H'FFFF87 is reserved.
Reserved
The initial value should not be changed.
Internal Clock Source Select 1, 0
These bits select a clock to be input to the timer
counter (TCNT) and a count condition together with
bits CKS2 to CKS0 in the timer control register
(TCR). For details, see section 12.3.4, Timer Control
Register (TCR).
Rev. 3.00, 03/04, page 57 of 830