HD64F2168 Datasheet, PDF (164/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

6.5 Bus Interface
The normal extended bus interface enables direct connection to ROM and SRAM. For details on
selection of the bus specifications for the basic extended area, 256-kbyte extended area, and CP
extended area, see tables 6.4 to 6.6.
The address-data multiplex extended bus interface enables direct connection to products that
supports this bus interface. For details on selection of the bus specifications for the IOS extended
area, 256-kbyte extended area, and CP extended area, see tables 6.9 to 6.14.
6.5.1 Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The BSC has
a data alignment function, and controls whether the upper data bus (D15 to D8/AD15 to AD8) or
lower data bus (D7 to D0/AD7 to AD0) is used when the external address space is accessed,
according to the bus specifications for the area being accessed (8-bit access space or 16-bit access
space) and the data size.
(1) 8-Bit Access Space: Figure 6.3 illustrates data alignment control for the 8-bit access space.
With the 8-bit access space, the upper data bus (D15 to D8/AD15 to AD8) is always used for
accesses. The amount of data that can be accessed at one time is one byte: a word access is
performed as two byte accesses, and a longword access, as four byte accesses.
Byte size
Upper data bus Lower data bus
D15
D8 D7
D0
7
0
1st bus cycle
15
8
Word size
2nd bus cycle
7
0
1st bus cycle
31
24
Longword
2nd bus cycle
23
16
size
3rd bus cycle
15
8
4th bus cycle
7
0
Figure 6.3 Access Sizes and Data Alignment Control (8-bit Access Space)
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